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description gm384xa series is high performance with fixed-frequency current mode pwm controllers. they are specially de- signed for off-line and dc-to-dc converter applications. they require minimal external components to precisely tai- lor performance in a wide variety of applications. gm384xa series includes a trimmed oscillator for precise duty cycle control, a temperature-compensated reference, high gain error amplifier, a current-sensing comparator, and a high-current totem pole output for driving a power mosfet . on-chip protection features include undervoltage lockouts with hysteresis for both input and reference, cycle-by-cycle current limiting, programmable output deadtime, and a latch for single pulse metering. all these are in a simple dip-8 or sop-8 package! gm3842a and gm3844a have uvlo thresholds of 16v (on)/10v(off); gm3843a and gm3845a have uvlo thresh- olds of 8.4v (on)/ 7.6v (off). gm3842a and gm3843a oper- ate within 100% duty cycle; gm3844a and gm3845a oper- ate within 50% duty cycle. g m 4 3 1 features low start-up and operating current automatic feed forward compensation current mode operating frequency up to 500khz trimmed oscillator discharge current for precise duty cycle control latching pwm for cycle-by-cycle current limiting undervoltage lockout with hysteresis high current totem pole output the gm384xa have start-up current 0.17ma g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a www.gammamicro.com 1 simplified block diagram 1 2 4 8 5 6 7 3 5 7 + - error amplifier r r 5.0v reference v cc undervoltage lockout v ref undervoltage lockout oscillator latching pwm v cc v c output power ground current sense input v ref r/ c t t voltage feedback input output compensation gnd v 1 . 0
marking information & pin configura tions (top view) ordering number package shipping gm3842as8t GM3843AS8T gm3844as8t gm3845as8t gm3842as8r gm3843as8r gm3844as8r gm3845as8r gm3842ad8t gm3843ad8t gm3844ad8t gm3845ad8t sop - 8 sop - 8 sop - 8 sop - 8 sop - 8 sop - 8 sop - 8 sop - 8 dip-8 dip-8 dip-8 dip-8 100 units/ tube 100 units/ tube 100 units/ tube 100 units/ tube 2,500 units/ t ape & reel 2,500 units/ t ape & reel 2,500 units/ t ape & reel 2,500 units/ t ape & reel 60 units/ tube 60 units/ tube 60 units/ tube 60 units/ tube dip - 8 1 2 3 4 5 6 7 8 v cc v ref output gnd comp fb r / c tt i sense gm384x 2 g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a ordering information (green package products are available now!) sop - 8 1 2 3 4 5 6 7 8 v cc v ref output gnd comp fb r / c tt i sense gm384x * for detail ordering number identification, please see last page. ** for green package products, please add " g" at the end of each part number. ayww ayww a = assembly location y = y ear w w = weekly
package pin description function function comp gnd v fb output v ref i sense r/ c t t this pin is error amplifier output and is made available for loop compensation. this pin is the combined control circuitry and power ground. this pin is the positive supply of the control integrated circuit (ic) this is the inverting input of the error amplifier . it is normally connected to the switching power supply output through a resistor divider. this output directly drives the gate of a power mosfet . peak current up to 1.0a are sourced and sunk by this pin. this is the reference output. it provides charging current for capacitor c t through resistor r t. a voltage proportional to inductor current connected to this input. the pwm uses this information to terminate the output switch conduction. oscillator frequency and maximum output cycle are programmed by connecting resistor to v and capacitor c to ground. r t ref t pin lead 1 5 7 2 6 8 3 4 g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a 3 p ara met er sym bol v alu e uni t absolute maximum ratings supp ly v oltag e (low impe danc e sou rce) outp ut cu rrent , sou rce o r sin k * input vo ltage (ana log in puts pins 2) maxi mum pow er di ssipa tion ( t = 25 c) a error am p ou tput s ink c urren t stora ge t empe ratur e ran ge lead t empe ratur e (so lderin g 5 s ec.) 30 1.0 - 0.3 to + 5 .5 10 v a c c v cc i o v i p d i sink(e .a) t stg t l 1.0 - 65 to + 1 50 260 w ma v * note: maximum package power dissipation limits must be observed. v cc
power management g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a 4 representa tive block diagram v cc v in v cc 7 v c output 7 6 q1 5 power ground 3 current sense input r s 36v + - + - v cc uvlo reference regulator v ref uvlo + - 3.6v internal baias r r oscillator 2.5v 8 4 v ref r t c t 2 1 voltage feedback input output compensation + 1.0ma + - + - error amplifier 2r r 1.0v 5 gnd current sense comparator - + pwm latch s r q q t + - + - = sink only positive true logic (toggle flip flop used only in gm3844a, gm3845a) capacitor c t latch "set" input output/ compensation current sense input latch "reset" input output latch r / small c t t small / latch c t t r timing diagram 1/2 v ref
g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a 5 electrical characteristics (t = 0c to 70c, *v =15v, c =3.3nf, r =10k w , unless otherwise specified ) ac c t t typ max unit characteristics test conditions min symbol reference section oscillator section error amplifier section current sense section output section undervoltage lockout section reference output voltage oscillation frequency input bias current curren t sens e inpu t vo ltage g ain rise time fall time low output voltage start threshold high output voltage minimum operating voltage (after tum on) line regulation frequency change with voltage input voltage maximum input signal load regulation oscillator amplitude open loop voltage gain supply voltage rejection power supply rejection ratio input bias current output sink current output source current high output voltage low output voltage short circuit output current v ref f d v ref d f/ d v cc v i(ea) v i(max) d v ref v (osc) a vol svr psrr i sc t = 25c, i = 1ma j ref t = 25c j v = 3v fb (note 1 and 2) t = 25c, c = 1nf(note 3) jl t = 25c, c = 1nf(note 3) jl i = 20ma sink gm3842a, gm3844a i = 20ma source gm3842a, gm3844a 4.9 47 5.0 52 -0.1 3.0 45 35 0.08 16.0 13.5 10 6.0 6.0 1.6 90 70 70 -3.0 7 -1.0 6.0 0.8 -100 5.1 57 -2 3.15 150 150 0.4 17.5 20 1.0 2.58 1.1 2.2 9.0 25 -180 v khz a v/ v ns ns mv % v v v v v v mv v db db db a ma 12v v 25v cc 12v v 25v cc v =2.5v pin1 v =5v (note 1) pin1 i = 200ma sink gm3843a, gm3845a i = 200ma source gm3843a, gm3845a 1ma 20ma i ref (peak to peak) t =25c a 0.05 2.5 1.0 1.4 8.4 13 7.6 i bias g v t r t f v ol v th(st) v oh v opr(min) 2v v 4v o 65 60 2 -0.5 5.0 12v v 25v cc v =2.7v, pin2 v =1.1v pin1 v =2.3v, pin2 v =5v pin1 v =2.3v, r pin2 =15k w to gnd l v =2.7v, r pin2 =15k w to pin8 l i sink i source v oh v ol ma ma v v 1.1 2.85 0.9 12v v 25v (note 1) cc i bias v =3v pin3 -10 13 8.5 12 7.0 14.5 7.8 11.5 8.2 2.42
6 g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a electrical characteristics (continued) (t = 0c to 70c, *v =15v, c =3.3nf, r =10k w , unless otherwise specified ) ac c t t typ max unit characteristics test conditions min symbol pwm section total standby current maximum duty cycle minimum duty cycle zener voltage operating supply current start-up current d (max) d (min) v z i cc(opr) i st gm3842a, gm3843a gm3844a, gm3845a 95 47 97 48 100 50 0 17 0.3 % % v ma ma v = =0v pin3 v pin2 i = 25ma cc 30 38 13 0.17 * adjust v above the startup threshold before setting to 15 v. cc note1: parameter measured at trip point of latch with v = 0. pin2 note2: gain defined as a= d v / d v ; 0 v 0.8v pin1 pin3 pin3 note3: these parameters, although guaranteed, are not 100% tested in production typical performance characteristics 50 20 10 1 2 5 10 20 30 50 100 200 300 500 r t (k w ) fosc (khz) v = 15v cc t =25c a figure 1. timing resistor vs. oscillator frequency c = 1000pf t c = 200pf t c = 500pf t c = 10pf t c = 5nf t c = 2nf t c = 1nf t 50 20 10 1 2 5 10 20 30 50 100 200 300 500 % fosc (khz) v = 15v cc t =25c a figure 2. output dead-time vs. oscillator frequency c = 1000pf t c = 200pf t c = 5nf t c = 2nf t c = 1nf t c = 500pf t c = 10pf t 30 3 % gm3842a/ 43a/ 44a/ 45a
g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a 7 typical performance characteristics 90 80 70 60 50 40 1 2 3 5 r ( k w ) t dmax (%) figure 3. maximum output duty cycle vs. timing resistor (gm3842a/43a) v = 15v cc c = 3.3nf t =25c a t 80 60 40 20 0 -20 10 100 1k 10k 100k 1m f (hz) (db) figure 4. error amp open-loop gain vs. frequency v = 15v cc v = 2v to 4v r = 100k l t o = 25c a 1.0 0.8 0.6 0.4 0.2 0 2 4 6 v (v) o v th (v) figure 5. current sense input threshold vs. error amp output voltage 100 90 80 70 60 50 0 25 50 75 100 t (c) a i sc (ma) figure 6. reference short circuit current vs. temperature v = 15v cc t = 25c a t = 125c a -1 -2 3 2 1 0 0 200 400 600 i (ma) o v sat (v) figure 7. output saturation voltage vs. load current t = 25c a sourse saturation (load to ground) v = 15v cc 80s pulsed load 120hz rate sink saturation (load to v ) cc figure 8. supply current vs. supply voltage 20 15 10 5 0 0 10 20 30 v (v) cc i cc (ma) i = 0v sense v r = 0v fb = 10k t t = 25c a c = 3.3nf t g m 3 8 4 2 a / 4 4 a g m 3 8 4 3 a / 4 5 a v = 15v cc
operating description gm3842a, gm3843a, gm3844a and gm3845a are high performance with fixed frequency, current mode controllers. they are designed for off-ine and dc-to-dc converter applications offering great versatility with minimal external components. a representative block diagram is shown on page 4. oscillator the oscillator frequency is determined by the values of the timing components r and c . capacitor c is tt t charged from the 5.0 v reference through resistor r to approximately 2.8 v and discharged to 1.2 v by an t internal current sink. during the of c , the oscillator generates an internal blanking pulse that holds the center t input of the nor gate high. this causes the output to be in a low state, thus producing a controlled amount of figure 2 show r versus oscillator frequency and figure 2, output deadtime versus frequency, both for given t values of c output deadtime. t note that different values of r and c will give the same oscillator frequency, but only one combination will yield tt a specific output deadtime at a given frequency. the oscillator thresholds are temperature com pensated. these interned circuit vefinements minimizes refinements of oscillator frequency and maximum output duty cycle. in many noise sensitive applications, it may be desirable to frequency-lock the converter to an external system clock. this can be accmplished by applying a clock signal to the circuit shown in figure 9. for best locking results, set the free-unning oscillator frequency to about 10% less than the clock frequency. a method for multi unit synchronization is shown in figure 10. y ou can get very accurate output duty cycle clamping by tweaking the clock waveform. error amplifier gm384xa series has a fully compensated error amplifier with access to both the inverting input and output, and providing dc voltage gain of 90 db (typical). the noninverting input is internally biased at 2.5 v and is not pinned out. the converter output voltage is typically divided down and monitored by the inverting input. the maximum input bias current is -2.0 a, which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. the error amplifier output (pin 1) allows external loop compensation. the output voltage is offset by the two diode drops ( 1.4 v) and divided by three before it connects to the inverting input of the current sense comparator. this assures that no drive pulses appear at the output (pin 6) when pin 1 is at its lowest state (v ). this happens when the power supply is operating and the load is removed, or at the beginning of a soft- ol start interval (figures 11, 12). the error amp minimum feedback resistance is limited by the amplifier's source current (0.5 ma) and the required output voltage (v ) to reach the comparator's 1.0 v clamp level: oh current sense comparator and pwm latch gm384xa series operates as a current mode controller , whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the error amplifier output/compensation (pin1). the error signal controls the peak inductor current cycle-by-cycle basis. the current sense comparator pwm latch configuration assures that only a single pulse appears at the output during any given oscillator cycle. the inductor current is converted to a voltage by inserting the ground- referenced sense resistor r in series with the source of output switch q1. this voltage is monitored by the s current sense input (pin 3) and compared to a level derived from the error amp output. the peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: when the power supply output is overloaded or if output voltage sensing is lost, the chip operation is not normal. in these situations, the current sense comparator threshold will be internally clamped to 1.0 v and the maximum peak switch current is: r = 8800 w f(min) 3.0(1.0v) + 1.4v 0.5ma i= pk v - 1.4v (pin1) 3 r s i= pk(mak) 1.0v r s 8 g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a
when designing a high power switching regulator, it becomes desirable to reduce the internal clamp voltage in order, to keep a reasonable level of power dissipation of r . adjusting the internal clamp voltage is very simple, s as shown in figure 11. the two external diodes compensate the internal diodes so you get a constant clamp voltage over temperature. avoid too much reduction of the i clamp voltage, or you will get noise pickup and pk(max) erratic results. a narrow spike on the leading edge of the current waveform often occurs and can cause the power supply instability when the output load is light. this spike is caused by power transformer interwinding capacitance and output rectifier recovery time. y ou can eliminate this problem by adding an rc filter on the current sense input, with a time constant similar to the spike's duration; see figure 16. undervoltage lockout two uvlo comparators in gm384xa series assure that the chips are fully functional before the output stage is enabled. the positive power supply terminal (v ) and the reference output (v ) have separate comparators. cc ref each has built-in hysteresis to prevent erratic output behavior as their thresholds are reached. the v cc comparator's upper and lower thresholds are 16 v/10 v for gm3842a and gm3844a, and 8.4v/7.6v for gm3843a and gm3845a. the v comparator's upper and lower thresholds are 3.6v/3.4 v. the large hysteresis and low startup current of ref the gm3842a and gm3844a makes them ideal for off-line converter applications where efficient bootstrap startup is required. gm3843a and gm3845a are intended for lower voltage dc-to-dc converter applications. a 36 v zener is connected as a shunt regulator from v to ground. its purpose is to protect the ic from excessive voltage that cc can occur during system startup. the minimum operating voltage for gm3842a and gm3844a is 11v ; for gm3843a and gm3845a it is 8.2v. output gm384xa series has a single totem pole output stage that was designed for direct drive of power mosfet s. it provides up to 1.0 a peak drive current and has a typical rise/ fall time of 50 ns with a 1.0 nf load. additional internal circuitry keeps the output in a sinking mode whenever a uvlo is active. this eliminates the need for an external pull-down resistor. reference the 5.0 v bandgap reference is trimmed to 1.0% tolerance at t = 25c on the gm384xa series. its primary j purpose is to supply charging current to the oscillator timing capacitor. the reference has short circuit protection and it can provide more than 20ma for powering additional control system circuitry . design considerations do not make your converter to use wire-wrap or plug-in prototype boards. high-frequency circuit layout techniques must be observed to prevent pulsewidth jitter. this is usually caused by excessive noise pick-up imposed on the current sense or voltage feedback inputs. y ou can improve noice immunity by lowering circuit impedances at these points. the pcb layout should have a ground plane with low-current signal and high- current switch and output grounds returning on separate paths to the input filter capacitor. ceramic bypass capacitors (0.1 f) connected directly to v , v , and v may be required, depending upon circuit layout, to cc c ref provide a low impedance path for filtering high frequency noise. all high-current loops should be as short as possible and use heavy copper runs to minimize radiated emi. the error amp compensation circuitry and the converter output voltage divider should be placed as close as possible to the gm384xa, and as far as possible from the power switch and other noise- generating components. g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a 9
10 g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current. this instability is independent of the regulators closed?loop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. figure 9.a shows the phenomenon graphically. at t 0 , switch conduction begins and causes causing the inductor current to rise at a slope of m 1 . this slope is a function of the input voltage divided by the inductance. at t 1 , the current sense input reaches the threshold established by the control voltage. this causes the switch to turn off and the current to decay at a slope of m 2 until the next oscillator cycle. the unstable condition can be shown if a pertubation is added to the control voltage, and resulting in a small d i (dashed line). with a fixed oscillator period, the current decay time is reduced and the minimum current at switch turn?on (t 2 ) is increased by d i + d i m2/m1. the minimum current at next cycle (t 3 ) decreases to ( d i + d i m 2 /m 1 ) (m 2 /m 1 ). this pertubation is multiplied by m 2 .m 1 on each succeeding cycle, alternately increasing and decreasing the inductor current at switch turn?on. several oscillator cycles may be required before the inductor current reaches zero, which caused causing the process to commence again. if m 2 /m 1 is greater than 1, the converter will be unstable. figure 9.b shows that by adding an artificial ramp, that is synchronized with the pwm clock to the control voltage, the d i pertubation will decrease to zero on succeeding cycles. this compensation ramp (m 3 ) must have a slope equal to or slightly greater than m 2 /2 for stability. with m 2 /2 slope compensation, the average inductor current follows the control voltage yielding true current mode operation. the compensating ramp can be control voltage d i inductor current t 0 t 1 t 2 t 3 d i + d i m2 m2 m1 m1 m2 m1 ( d i + d i ) ( ) m2 m1 oscillator period a b control voltage d i oscillator period m1 m2 m3 inductor current t 4 t 5 t 6 figure 9. continuous current waveforms
8 4 2 1 5 + - error amplifier v ref r t c t 47 0.01 external sync input r r internal bias oscillartor 2r r + figure 10. external clock synchronization * the diode clamp is required if the sync amplitude is large enough to cause the bottom side of to go more than 300 mv below ground. c t + r a r b c 6 5 2 8 5.0k + - + - 5.0k 5.0k 1 4 r s q 3 7 8 4 2 1 r r internal bias oscillator + - error amplifier 2r r gnd 5 t o additional gm384xa series figure 11. external duty cycle clamp and multi-unit synchronization f= 1.44 (r + 2r ) c ab dmax r b r + 2r ab g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a 11
r2 8 4 2 1 r1 r r internal bias oscillator + - error amplifier 1.0ma v clamp + 2r r 5 1.0v - + s r + - + - 5.0 v ref v cc 7 + - v cc v in 7 6 5 3 r s q1 figure 12. adjustable reduction of clamp level t 3600c in f soft-start 8 4 2 1 5 c r r internal bias oscillator + - + - 5.0 v ref 2r 1.0ma + - + error amplifier r 1.0v + - q s r q figure 13. soft-start circuit + - comp/ latch 1.0m v = +0.33x10-3 ( ) clamp 1.67 ( + 1) r2 r1 r1 + r2 r1 + r2 i= pk(max) where: 0 v 1.0v clamp v clamp rs 12 g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a
8 4 2 1 r2 r1 c + - error amplifier r r internal bias oscillator 1.0ma 2r v calmp r 5 5.0 v ref + - + - + - + - v cc 7 v cc v in 7 6 5 3 + - r s q q1 r s comp/ latch 1.0v figure 14. adjustable buffered reduction of clamp level with soft-start 5.0 v ref + - + - + - + - 7 7 6 5 3 5 r 1.0v + - r s q v cc v in v cc r s sensefet d g m k s power ground to input source retum control circuitry ground comp/ latch figure 15. current sensing power mosfet for proper operation during over current conditions, a reduction of the ipk(max) clamp level must be implemented. refer to figures 11 and 12. 1/4w v= clamp 1.67 ( + 1) r2 r1 i= pk(max) where: 0 v 1.0v clamp t = -ln [ 1- ] softstart c v clamp rs v c 3v clamp r1 + r2 r1 + r2 v 5 = pin if= sensefet= mtp10n10m = 200 then : r s v 5= 0.075 l pin pk r i r s pk ds(on) rr ds(on) + s g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a 13 mpsa63
v cc v in v cc + - + - s r q q t + - + - 5.0 v ref 7 7 8 5 3 5 + - r q1 r s r comp/ latch 1.0v c * the addition of the r filter will eliminate instability caused by the leading edge spike on the current waveform. c figure 16. current wavefrom spike suppression 14 g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a
g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a 15 + - + - + - + - - + s r q 5.0 v ref comp/ latch v in v cc r g q1 r s 7 7 6 5 3 series gate resistor rg will damp any high frequency parasitic oscillations caused by the mosfet input capacitance and any series wiring inductance in the gate-source circuit. figure 17. mosfet parasitic oscillations + - + 1.0ma r 2r ea 2 1 5 r f c i r i r d v o figure 18. isolated mosfet drive error amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current. 2.5v
16 g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a + - + bias osc r r 1.0ma r 2r ea 2n3903 2n3905 mcr101 8 4 2 1 5 figure 19. latched shutdown the mcr101 scr must be selected for a holding of less than 0.5 ma at t (min). a the simple two transistor circuit can be used in place of the scr as shown. all resistors are 10 k. + - + 1.0ma r 2r ea 2 1 5 r f c i r i v o figure error amplifier compensation error amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current. 2.5v r d r p c p
g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a 17 0.275 7.0 0.155 4.0 0.060 1.52 0.050 1.270 0.024 0.6 inches mm ( ) pad layout 0 ~ 8 sop-8 p ackage outline dimensions pin indent 0.0285 0.0105 0.725 0.275 0.008 0.002 0.203 0.05 0.238 0.008 6.04 0.2 0.155 0.004 3.94 0.1 0.693 0.504 4.91 0.1 0.05 1.27 0.057 0.004 1.45 0.1 0.007 0.003 0.175 0.075 0.016 0.004 0.406 0.1 0.063 0.006 1.60 0.15 0.02 min 0.51 min dip-8 p ackage outline dimensions 0.362 0.008 9.20 0.2 0.018 0.004 0.46 0.10 0.06 0.006 1.524 0.15 inches mm ( ) 0.252 0.008 6.40 0.2 0.1 0.008 2.54 0.2 0.134 0.008 3.40 0.2 0.158 0.012 4.01 0.3 0.13 0.008 3.30 0.2 0.3 0.008 7.62 0.2 0.3425 0.0155 8.70 0.4 0.012 0.004 0.304 0.1
18 g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a ordering number gm 3842 a s8 r gamma micro. circuit type package s8: sop-8 d8: dip-8 shipping r: t ape & reel "a" version
g m 3 8 4 2 a , g m 3 8 4 3 a , g m 3 8 4 4 a , g m 3 8 4 5 a 19

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